Exploring MLIR-Based Lowering Paths for OPS Stencil Applications on FPGAs

Exploring MLIR-Based Lowering Paths for OPS Stencil Applications on FPGAs

Compiler Frameworks

Ali Aljeshi

Gihan Mudalige

Recent work has shown that FPGA accelerators can achieve high performance and energy efficiency for stencil-based solvers using automatic code generation and High-Level Synthesis (HLS). The OPS (Oxford Parallel library for Structured mesh solvers) DSL demonstrates this by analysing iterative stencil loops and generating deeply pipelined FPGA designs with domain-specific optimisations. The current OPS FPGA backend implements these optimisations through a custom code-generation pipeline, but embeds compiler logic directly within the code generator rather than using an explicit intermediate representation. Multi-Level Intermediate Representation (MLIR) provides a more structured approach, allowing programs to be represented and progressively lowered between abstraction levels while making the compiler more maintainable and extensible. This research aims to investigate MLIR-based lowering strategies for OPS stencil applications targeting FPGAs, exploring existing infrastructure and how it could be extended to support a broader range of applications.

Compilers, Computer Science, FPGAs, Stencil Computations, Domain Specific Language,